View FM1608-120-PG_1356937.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

n o t r e c o m m e n d e d f o r n e w d e s i g n s a l t e rn a t i v e s : f m 1 6 0 8 b o r f m 1 6 w 0 8 this product conforms to specifications per the terms of the ramtron ramtron international corporation standard warranty. the product has completed ramtron?s internal 1850 ramtron drive, colorado springs, co 80921 qualification testing and has reached production status. (800) 545-fram, (719) 481-7000 http://www.ramtron.com rev. 3.4 nov. 2010 1 of 12 fm1608 64kb bytewide f-ram memory features 64k bit ferroelectric nonvolatile ram ? organized as 8,192 x 8 bits ? high endurance 1 trillion (10 12 ) read/writes ? 45 year data retention ? nodelay? writes ? advanced high-reliability ferroelectric process superior to bbsram modules ? no battery concerns ? monolithic reliability ? true surface mount solution, no rework steps ? superior for moisture, shock, and vibration ? resistant to negative voltage undershoots sram & eeprom compatible ? jedec 8kx8 sram & eeprom pinout ? 120 ns access time ? 180 ns cycle time low power operation ? 15 ma active current ? 20 a standby current industry standard configuration ? industrial temperature -40 c to +85 c ? 28-pin soic or dip ? ?green?/rohs packaging description the fm1608 is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory or f-ram is nonvolatile but operates in other respects as a ram. it provides data retention for 45 years while eliminating the reliability concerns, functional disadvantages and system design complexities of battery-backed sram. its fast write and high write endurance make it superior to other types of nonvolatile memory. in-system operation of the fm1608 is very similar to other ram based devices. minimum read- and write- cycle times are equal. the f-ram memory, however, is nonvolatile due to its unique ferroelectric memory process. unlike bbsram, the fm1608 is a truly monolithic nonvolatile memory. it provides the same functional benefits of a fast write without the serious disadvantages associated with modules and batteries or hybrid memory solutions. these capabilities make the fm1608 ideal for nonvolatile memory applications requiring frequent or rapid writes in a bytewide environment. the availability of a true surface-mount package improves the manufacturability of new designs, while the dip package facilitates simple design retrofits. the fm1608 offers guaranteed operation over an industrial temperature range of -40c to +85c. pin configuration ordering information FM1608-120-PG 120 ns access, 28-pin ?green? dip fm1608-120-sg 120 ns access, 28-pin ?green? soic nc a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 vss dq3 dq4 dq5 dq6 dq7 ce a10 oe a11 a9 a8 nc we vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
n o t r e c o m m e n d e d f o r n e w d e s i g n s a l t e rn a t i v e s : f m 1 6 0 8 b o r f m 1 6 w 0 8 fm1608 rev. 3.4 nov. 2010 2 of 12 address latch a0-a12 ce control logic we row decoder block decoder column decoder a0-a7 a8-a9 a10-a12 i/o latch bus driver oe 8,192 x 8 fram array dq0-7 figure 1. block diagram pin description pin name i/o pin description a0-a12 input address: the 13 address inputs select one of 8,192 bytes in the f-ram array. the address value will be latched on the falling edge of /ce. dq0-7 i/o data: 8-bit bi-directional data bus for accessing the f-ram array. /ce input chip enable: /ce selects the device when low. asserting /ce low causes the address to be latched internally. address changes that occur after /ce goes low will be ignored until the next falling edge occurs. /oe input output enable: asserting /oe low causes the fm1608 to drive the data bus when valid data is available. deasserting /oe high causes the dq pins to be tri-stated. /we input write enable: asserting /we low causes the fm1608 to write the contents of the data bus to the address location latched by the falling edge of /ce. vdd supply supply voltage: 5v vss supply ground. functional truth table /ce /we function h x standby/precharge x latch address (and begin write if /we=low) l h read l write note: the /oe pin controls only the dq output buffers.
n o t r e c o m m e n d e d f o r n e w d e s i g n s a l t e rn a t i v e s : f m 1 6 0 8 b o r f m 1 6 w 0 8 fm1608 rev. 3.4 nov. 2010 3 of 12 overview the fm1608 is a bytewide f-ram memory. the memory array is logically organized as 8,192 x 8 and is accessed using an industry standard parallel interface. the fm1608 is inherently nonvolatile via its unique ferroelectric process. all data written to the part is immediately nonvolatile with no delay. functional operation of the f-ram memory is the same as sram type devices, except the fm1608 requires a falling edge of /ce to start each memory cycle. memory architecture users access 8,192 memory locations each with 8 data bits through a parallel interface. the 13-bit address specifies each of the 8,192 bytes uniquely. internally, the memory array is organized into 8 blocks of 1kb each. the 3 most-significant address inputs decode one of 8 blocks. this block segmentation has no effect on operation, however the user may wish to group data into blocks by its endurance requirements as explained in a later section. the cycle time is the same for read and write memory operations. this simplifies memory controller logic and timing circuits. likewise the access time is the same for read and write memory operations. when /ce is deasserted high, a precharge operation begins, and is required of every memory cycle. thus unlike sram, the access and cycle times are not equal. writes occur immediately at the end of the access with no delay. unlike an eeprom, it is not necessary to poll the device for a ready condition since writes occur at bus speed. note that the fm1608 has no special power-down demands. it will not block user access, and it contains no power-management circuits other than a simple internal power-on reset. it is the user?s responsibility to ensure that vdd is within datasheet tolerances and to ensure the proper voltage level and timing relationship between vdd and /ce in power-up and power-down events to prevent incorrect operation. memory operation the fm1608 is designed to operate in a manner very similar to other bytewide memory products. for users familiar with bbsram, the performance is comparable but the bytewide interface operates in a slightly different manner as described below. for users familiar with eeprom, the obvious differences result from the higher write performance of f-ram technology including nodelay writes and much higher write endurance. read operation a read operation begins on the falling edge of /ce. at this time, the address bits are latched and a memory cycle is initiated. once started, a complete memory cycle must be completed internally regardless of the state of /ce. data becomes available on the bus after the access time has been satisfied. after the address has been latched, the address value may change upon satisfying the hold time parameter. unlike an sram, changing address values will have no effect on the memory operation after the address is latched. the fm1608 will drive the data bus when /oe is asserted low. if /oe is asserted after the memory access time has been satisfied, the data bus will be driven with valid data. if /oe is asserted prior to completion of the memory access, the data bus will not be driven until valid data is available. this feature minimizes supply current in the system by eliminating transients caused by invalid data being driven onto the bus. when /oe is inactive the data bus will remain tri-stated. write operation writes occur in the fm1608 within the same time interval as reads. the fm1608 supports both /ce- and /we-controlled write cycles. in both cases, the address is latched on the falling edge of /ce. in a /ce-controlled write, the /we signal is asserted prior to beginning the memory cycle. that is, /we is low when /ce falls. in this case, the part begins the memory cycle as a write. the fm1608 will not drive the data bus regardless of the state of /oe. in a /we-controlled write, the memory cycle begins on the falling edge of /ce. the /we signal falls after the falling edge of /ce. therefore the memory cycle begins as a read. the data bus will be driven according to the state of /oe until /we falls. the timing of both /ce- and /we-controlled write cycles is shown in the electrical specifications section. write access to the array begins asynchronously after the memory cycle is initiated. the write access terminates on the rising edge of /we or /ce, whichever is first. data set-up time, as shown in the electrical specifications, indicates the interval during which data cannot change prior to the end of the write access.
n o t r e c o m m e n d e d f o r n e w d e s i g n s a l t e rn a t i v e s : f m 1 6 0 8 b o r f m 1 6 w 0 8 fm1608 this product conforms to specifications per the terms of the ramtron ramtron international corporation standard warranty. the product has completed ramtron?s internal 1850 ramtron drive, colorado springs, co 80921 qualification testing and has reached production status. (800) 545-fram, (719) 481-7000 http://www.ramtron.com rev. 3.4 nov. 2010 4 of 12 unlike other truly nonvolatile memory technologies, there is no write delay with f-ram. since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. the entire memory operation occurs in a single bus cycle. therefore, any operation including read or write can occur immediately following a write. data polling, a technique used with eeproms to determine if a write is complete, is unnecessary. precharge operation the precharge operation is an internal condition that prepares the memory for a new access. all memory cycles consist of a memory access and a precharge. the precharge is initiated by deasserting the /ce pin high. it must remain high for at least the minimum precharge time t pc . the user dictates the beginning of this operation since a precharge will not begin until /ce rises. however the device has a maximum /ce low time specification that must be satisfied. endurance the fm1608 internally operates with a read and restore mechanism. therefore, each read and write cycle involves a change of state. the memory architecture is based on an array of rows and columns. each read or write access causes an endurance cycle for an entire row. in the fm1608, a row is 32 bits wide. every 4-byte boundary marks the beginning of a new row. endurance can be optimized by ensuring frequently accessed data is located in different rows. regardless, f-ram offers substantially higher write endurance than other nonvolatile memories. the rated endurance limit of 10 12 cycles will allow 3000 accesses per second to the same row for 10 years. f-ram design considerations when designing with f-ram for the first time, users of sram will recognize a few minor differences. first, bytewide f-ram memories latch each address on the falling edge of chip enable. this allows the address bus to change after starting the memory access. since every access latches the memory address on the falling edge of /ce, users cannot ground it as they might with sram. users who are modifying existing designs to use f- ram should examine the memory controller for timing compatibility of address and control pins. each memory access must be qualified with a low transition of /ce. in many cases, this is the only change required. an example of the signal relationships is shown in figure 2 below. also shown is a common sram signal relationship that will not work for the fm1608. the reason for /ce to strobe for each address is two- fold: it latches the new address and creates the necessary precharge period while /ce is high.
n o t r e c o m m e n d e d f o r n e w d e s i g n s a l t e rn a t i v e s : f m 1 6 0 8 b o r f m 1 6 w 0 8 n o t r e c o m m e n d e d f o r n e w d e s i g n s a l t e rn a t i v e s : f m 1 6 0 8 b o r f m 1 6 w 0 8 fm1608 rev. 3.4 nov. 2010 5 of 12 figure 2. memory address and /ce relationships a second design consideration relates to the level of v dd during operation. battery-backed srams are designed to monitor v dd in order to switch to battery backup. they typically block user access below a certain v dd level in order to minimize battery drain from an otherwise active sram. the user can be abruptly cut off from access to the memory in a power down situation without warning. f-ram memories do not need this system overhead. the memory will not block access at any v dd level. the user, however, should prevent the processor from accessing memory when v dd is out-of-tolerance. the common design practice of holding a processor in reset during powerdown may be sufficient. it is recommended that chip enable is pulled high and allowed to track v dd during powerup and powerdown cycles. it is the user?s responsibility to ensure that chip enable is high to prevent accesses below v dd min. (4.5v). figure 3 shows a pullup resistor on /ce which will keep the pin high during power cycles assuming the mcu/mpu pin tri-states during the reset condition. the pullup resistor value should be chosen to ensure the /ce pin tracks v dd yet a high enough value that the current drawn when /ce is low is not an issue. figure 3. use of pullup resistor on /ce ce we oe a(12:0) dq fm1608 v dd mcu/ mpu r
n o t r e c o m m e n d e d f o r n e w d e s i g n s a l t e rn a t i v e s : f m 1 6 0 8 b o r f m 1 6 w 0 8 n o t r e c o m m e n d e d f o r n e w d e s i g n s a l t e rn a t i v e s : f m 1 6 0 8 b o r f m 1 6 w 0 8 fm1608 rev. 3.4 nov. 2010 6 of 12 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss -1.0v to +7.0v v in voltage on any pin with respect to v ss -1.0v to +7.0v and v in < v dd +1.0v t stg storage temperature -55 c to + 125 c t lead lead temperature (soldering, 10 seconds) 300 c v esd electrostatic discharge voltage - human body model (jedec std jesd22-a114-b) - machine model (jedec std jesd22-a115-a) 4kv 300v package moisture sensitivity level msl-1 (-sg) 1 msl-2 (-sg) 2 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliabilit y. 1. applies to devices marked with date code 0627 and higher. 2. applies to devices marked with date code prior to 0627. dc operating conditions (t a = -40 c to + 85 c, v dd = 4.5v to 5.5v unless otherwise specified) symbol parameter min typ max units notes v dd power supply 4.5 5.0 5.5 v i dd1 vdd supply current ? active 5 15 ma 1 i sb1 standby current ? ttl 400 a 2 i sb2 standby current ? cmos 7 20 a 3 i li input leakage current 10 a 4 i lo output leakage current 10 a 4 v ih input high voltage 2.0 v dd + 0.3 v v il input low voltage -0.3 0.8 v v oh output high voltage (i oh = -2.0 ma) 2.4 - v v ol output low voltage (i ol = -4.2 ma) - 0.4 v notes 1. v dd = 5.5v, /ce cycling at minimum cycle time. all inputs at cmos levels, all outputs unloaded. 2. v dd = 5.5v, /ce at v ih , all other pins at ttl levels. 3. v dd = 5.5v, /ce at v ih , all other pins at cmos levels. 4. v in , v out between v dd and v ss . data retention (v dd = 4.5v to 5.5v unless otherwise specified) parameter min units notes data retention 45 years
n o t r e c o m m e n d e d f o r n e w d e s i g n s a l t e rn a t i v e s : f m 1 6 0 8 b o r f m 1 6 w 0 8 n o t r e c o m m e n d e d f o r n e w d e s i g n s a l t e rn a t i v e s : f m 1 6 0 8 b o r f m 1 6 w 0 8 fm1608 rev. 3.4 nov. 2010 7 of 12 read cycle ac parameters (t a = -40 c to + 85 c, v dd = 4.5v to 5.5v unless otherwise specified) symbol parameter min max units notes t ce chip enable access time ( to data valid) 120 ns t c a chip enable active time 120 2,000 ns t rc read cycle time 180 ns t pc precharge time 60 ns t as address setup time 0 ns t ah address hold time 10 ns t oe output enable access time 10 ns t hz chip enable to output high-z 15 ns 1 t ohz output enable to output high-z 15 ns 1 write cycle ac parameters (t a = -40 c to + 85 c, v dd = 4.5v to 5.5v unless otherwise specified) symbol parameter min max units notes t c a chip enable active time 120 2,000 ns t cw chip enable to write high 120 ns t wc write cycle time 180 ns t pc precharge time 60 ns t as address setup time 0 ns t ah address hold time 10 ns t wp write enable pulse width 40 ns t ds data setup 40 ns t dh data hold 0 ns t wz write enable low to output high z 15 ns 1 t wx write enable high to output driven 10 ns 1 t hz chip enable to output high-z 15 ns 1 t ws write setup 0 ns 2 t wh write hold 0 ns 2 notes 1 this parameter is periodically sampled and not 100% tested. 2 the relationship between /ce and /we determines if a /ce- or /we-controlled write occurs. there is no timing specification associated with this relationship. power cycle timing (t a = -40 c to + 85 c, v dd = 4.5v to 5.5v unless otherwise specified) symbol parameter min max units notes t pu v dd (min) to first access start 1 - s t pd last access complete to v dd (min) 0 - s
n o t r e c o m m e n d e d f o r n e w d e s i g n s a l t e rn a t i v e s : f m 1 6 0 8 b o r f m 1 6 w 0 8 n o t r e c o m m e n d e d f o r n e w d e s i g n s a l t e rn a t i v e s : f m 1 6 0 8 b o r f m 1 6 w 0 8 fm1608 rev. 3.4 nov. 2010 8 of 12 capacitance (t a = 25 c , f=1.0 mhz, v dd = 5v) symbol parameter max units notes c i/o input/output capacitance (dq) 8 pf c in input capacitance 6 pf ac test conditions input pulse levels 0 to 3v input rise and fall times 10 ns input and output timing levels 1.5v read cycle timing /ce-controlled write cycle timing equivalent ac load circuit
n o t r e c o m m e n d e d f o r n e w d e s i g n s a l t e rn a t i v e s : f m 1 6 0 8 b o r f m 1 6 w 0 8 n o t r e c o m m e n d e d f o r n e w d e s i g n s a l t e rn a t i v e s : f m 1 6 0 8 b o r f m 1 6 w 0 8 fm1608 rev. 3.4 nov. 2010 9 of 12 /we-controlled write cycle timing power cycle timing v ih (min) t pd t pu v dd ce v il (max) v dd (min) t pc v dd (min) v ih (min) v ih (min) v ih (min) t pd t pd t pu t pu v dd ce v il (max) v il (max) v dd (min) v dd (min) t pc t pc v dd (min) v dd (min) v ih (min) v ih (min)
n o t r e c o m m e n d e d f o r n e w d e s i g n s a l t e rn a t i v e s : f m 1 6 0 8 b o r f m 1 6 w 0 8 n o t r e c o m m e n d e d f o r n e w d e s i g n s a l t e rn a t i v e s : f m 1 6 0 8 b o r f m 1 6 w 0 8 fm1608 rev. 3.4 nov. 2010 10 of 12 28-pin soic (jedec ms-013 variation ae) all dimensions in millimeters pin 1 7.50 0.10 10.30 0.30 17.90 0.20 0.10 0.30 2.35 2.65 0.33 0.51 1.27 typ 0.10 0.25 0.75 45 0.40 1.27 0.23 0.32 0? - 8? soic package marking scheme legend: xxxx= part number, s=speed (-120), p= package type (-pg, -sg) r=rev code, yy=year, ww=work week, llllll= lot code example: fm1608, 120ns speed, ?green?/rohs soic package, m die rev., year 2007, work week 11, lot code 70085g ramtron fm1608-120-sg m071170085g ramtron xxxxxxx-s-p ryywwlllllll
n o t r e c o m m e n d e d f o r n e w d e s i g n s a l t e rn a t i v e s : f m 1 6 0 8 b o r f m 1 6 w 0 8 n o t r e c o m m e n d e d f o r n e w d e s i g n s a l t e rn a t i v e s : f m 1 6 0 8 b o r f m 1 6 w 0 8 fm1608 rev. 3.4 nov. 2010 11 of 12 28-pin dip (jedec ms-011) all dimensions in inches 0.485 0.580 1.380 1.565 0.015 min. 0.100 bsc 0.005 min. 0.125 0.195 0.250 max 0.600 bsc 0.700 max. 0.600 0.625 0.030 0.070 pin 1 0.014 0.022 0.115 0.200 dip package marking scheme legend: xxxx= part number, s=speed (-120), p= package type (-pg, -sg) r=rev code, yy=year, ww=work week, llllll= lot code example: fm1608, 120ns speed, ?green?/rohs dip package, m rev., year 2007, work week 11, lot code 70085g ramtron FM1608-120-PG m071170085g ramtron xxxxxxx-s-p ryywwlllllll
n o t r e c o m m e n d e d f o r n e w d e s i g n s a l t e rn a t i v e s : f m 1 6 0 8 b o r f m 1 6 w 0 8 n o t r e c o m m e n d e d f o r n e w d e s i g n s a l t e rn a t i v e s : f m 1 6 0 8 b o r f m 1 6 w 0 8 fm1608 rev. 3.4 nov. 2010 12 of 12 revision history revision date summary 3.0 11/16/2004 removed power down sequence diagram and associated timing parameters. date codes 0435 and later are not affected by brownout conditions. updated footer to comply with new datasheet change procedure. removed applications section. 3.1 10/3/2006 removed -p and -s packaging options which are not recommended for new designs. extended data retention to 45 years. added esd and msl ratings. added recommendation on ce pin during power cycles. 3.2 5/30/2007 redraw package outlines, added marking scheme. 3.3 12/18/2007 updated msl ratings. 3.4 11/22/2010 not recommended for new designs. alternative devices: fm1608b, fm16w08.

▲Up To Search▲

Price & Availability of FM1608-120-PG

	To Download FM1608-120-PG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .